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真是大事,Global Foundry退出7nm製程競賽了!

蚵仔麵線好吃

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蚵仔麵線好吃

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文章編號：73906835

蚵仔麵線好吃 wrote:
台積電Q2營收超標...(恕刪)

台積電第二季營收超標下半年唱旺
https://www.chinatimes.com/newspapers/20190711000233-260202?chdtv

晶圓代工龍頭台積電受惠於華為海思擴大下單，16奈米與更先進製程晶圓出貨暢旺，加上新台幣兌美元匯率5月以來走貶，公告6月合併營收858.68億元，第二季合併營收季增10.2％、達2,409.99億元，雙雙優於預期，並超越先前在法說會上提出的2,329～2,360億元業績展望。

隨下半年7奈米製程貢獻到位，市場對台積電第三季營收季成長共識來到15～20％，樂觀看待股價表現。花旗環球證券半導體產業分析師徐振志指出，進入第三季傳統旺季，預期台積電16與7奈米製程產能利用率將會滿載，且第四季因華為訂單回籠，7奈米產能利用率將持續滿檔，下半年營運上檔可期。

台積電第二季表現優於預期，原因包括第一季因光阻原料影響良率導致報廢的晶圓於第二季補足及出貨，以及華為被美國商務部列入禁止出口實體清單後，華為海思擴大對台積電下單。

另外，隨智慧型手機生產鏈晶片庫存去化結束，Android陣營手機相關晶片訂單在5月及6月回流，推升台積電成熟製程及先進製程產能利用率。

台積電近期受到輝達下單三星消息影響，股價較為波動，不過，瑞銀證券亞太區半導體首席分析師呂家璈指出，台積電的7奈米製程無論在晶圓產能、市占率表現，都將能媲美當時取得莫大成功的28奈米製程，而且7奈米製程還享有CPU與人工智慧特殊應用晶片（AI ASIC）新商機，這也意味台積電7奈米製程仍將是客戶首選。外資並認為，包括蘋果、聯發科、華為、超微（AMD）、高通，以及其餘IDM廠委外代工，都將持續驅動台積電的營收獲利成長。

台積電將在18日召開第二季法人說明會，預期董事長劉德音將出席，並針對半導體市場下半年展望提出看法。法人表示，台積電第三季會有旺季效應，且劉德音在股東常會中也提及，今年下半年業績表現會優於去年下半年，所以，若台積電在法說會中維持今年全年美元營收較去年持平或小幅成長展望不變，對股價表現將可正面看待。

台積電第二季開始加快推進先進製程，導入極紫外光（EUV）技術的7+奈米已進入量產，針對5奈米打造的Fab 18第一期工程也進入試產階段。台積電下半年資本支出將明顯提高，5奈米製程應可如期在明年中量產投片，優化7奈米推出的6奈米製程明年底前進入量產的計畫不變。業界分析，台積電今、明兩年的資本支出可望放大，3奈米技術研發可望在明年完成生態系統建置，在晶圓代工市場拉開與競爭同業的技術差距

健人就是腳勤

蚵仔麵線好吃

13528分

樓主

蚵仔麵線好吃

個人積分：13528分

文章編號：73907052

蚵仔麵線好吃 wrote:
台積電第二季營收超...(恕刪)

〈日韓貿易戰〉正式啟動！日本從嚴辦理對韓出口光阻劑、高純度氟化氫等上榜
https://news.cnyes.com/news/id/4351038

日本政府從嚴管理出口到韓國的半導體先進材料，相關措施在週四 (4 日) 正式啟動。雖然韓國方面要求撤回，但日本以過去在可轉用到軍事用途的原物料方面，曾多次發生不當出口案例為由，堅持在出口管理上採取嚴格手段。

自 7 月 4 日起，日本政府在出口到韓國的氟化聚醯亞胺、光阻劑、高純度氟化氫等三種，在 OLED 面板及半導體生產不可或缺的先進原料，採取嚴格的出口管制。

----------------------

印象中台積電用的光阻都是日本貨:

AZ
信越
東京應化
住友

其實台灣也有生產光阻
只是用於面板
佔有率不高

---------------------------

這是日韓的貿易戰
台積電應佔到了好處

三星則是元氣大傷
三星的半導體用的光阻
也與台積電差不多都是日本貨

然後
高純度氟化氫
水溶液就是氫氟酸
用來蝕刻二氧化矽用的
濕製程用氫氟酸...

半導體製程
很多介電層
都是二氧化矽的相關化合物
如磷矽玻璃(PSG),硼磷矽玻璃(BPSG)
這些蝕刻液免不了要用到氟化氫

沒有日本的光阻與氟化氫
韓國的半導體產業會快完蛋

至於
氟化聚醯亞胺
就是polyimide簡稱PI膜
可撓式AMOLED的外層就是PI膜
像曲面玻璃底下的AMOLED就是可撓式AMOLED
工研院也會做
台灣的達邁也會做
但PI日本人做的最好

PI的重點在耐溫
耐溫很重要
因為 AMOLED上面也會有金屬導線
這些用濺鍍(sputtering)還是用蒸鍍的方法
一般溫度要250度
所以PI要耐溫300度以上
阿本仔的PI最好~

這是工研院研發可撓式顯示器的PI膜的介紹
如果要大量生產品質均一,那就要有量產的技術

所以三星的半導體與顯示器都會受到毀滅的打擊...

日韓再戰下去
台積電就... ^++^

健人就是腳勤

蚵仔麵線好吃

13528分

樓主

蚵仔麵線好吃

個人積分：13528分

文章編號：73970865

AMD登13年高！新CPU大熱銷、日韓市佔超車Intel
https://www.moneydj.com/KMDJ/News/NewsViewer.aspx?a=1842d771-1ed3-42be-ae92-4b73201c5d7c&c=MB07

MoneyDJ新聞 2019-07-16 10:40:42 記者陳苓報導

AMD新一代電腦處理器「Ryzen 3000」系列，搶在英特爾(Intel)之前採用7奈米製程，運算功能強大。開賣短短幾天以來，日韓市占率已經超車英特爾，科技網站也好評聲不斷，激勵AMD股價強彈。

嘉實XQ全球贏家系統報價顯示，週一(15日)AMD上漲3.55%收34.39美元，創2006年5月19日以來收盤新高。今年至今AMD股價暴衝86.29%。

Tom`s Hardware、wccftech、PCWorld、Barron`s報導，AMD本月7日發布第三代桌電處理器Ryzen 3000，採用Zen 2架構，並委請台積電(2330)以7奈米製程生產。Ryzen 3000是消費用的X86 CPU首次採用7奈米製程，計算效能更強、更為省電、並有更多核心，對採用14奈米製程的英特爾CPU帶來巨大挑戰。

7日開賣當天，粉絲排隊搶購Ryzen 3000。美國3C商家Micro Center證實，許多門市一早就出現人龍。日本秋葉原也有科技迷冒雨排隊。Moor Insights and Strategy分析師Patrick Moorhead說，消費者排隊等待購買PC零件的盛況，已經好幾年沒見了。剛上架前幾天，亞馬遜網站的Ryzen 3000一度賣到沒貨。

南韓零售巨擘Danawa旗下的Danawa Research數據顯示，Ryzen 3000開賣後，AMD CPU銷售增幅從一天前的28.24%、升至48.72%。兩天後AMD CPU銷量就壓倒英特爾，市佔達53.36%、勝過英特爾的46.64%。日本的BCN Ranking情況也差不多，日本AMD Ryzen市佔達50.5%、優於英特爾的49.5%。

Rosenblatt Securities分析師Hans Mosesmann對AMD極為樂觀，週一(15日)報告稱，AMD處於巨大產品週期的初期階段，重申買進評等。AMD今年至今漲幅接近90%，是標普500指數中，表現最突出的個股。

＊編者按：本文僅供參考之用，並不構成要約、招攬或邀請、誘使、任何不論種類或形式之申述或訂立任何建議及推薦，讀者務請運用個人獨立思考能力，自行作出投資決定，如因相關建議招致損失，概與《精實財經媒體》、編者及作者無涉。

健人就是腳勤

蚵仔麵線好吃

13528分

樓主

蚵仔麵線好吃

個人積分：13528分

文章編號：75162166

01新的版面看了很不習慣
所以就有點懶得更新

最近最熱的就是台積電的5nm製程了~

台積電的研發團隊是兩隊輪流上陣的
不然哪有可能馬上兩年就一代
每個team是搞個四年以上,而不是兩年...
5nm這個node還找空降來一起研發

台積電近5 個高階製程世代，都是由資深研發處長吳顯揚和曹敏輪流領軍(現在他們都升研發副總了)，分別負責隔代先進製程技術研發，其中，吳顯揚負責台積電16、7 奈米製程開發，曹敏則負責20、10 奈米製程世代，然台積電在5 奈米製程技術研發，由前高通資深製程技術處長Geoffrey Yeap 負責5 奈米技術開發。

Yeap將在今年的12月的IEDM(全世界最有名的元件國際研討會)發表TSMC的5nm製程演講:

5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and High-Mobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications

根據網路上的消息:
TSMC to Discuss Their 5-nm CMOS Technology Platform at IEDM 2019
https://www.semiconductor-digest.com/2019/10/14/tsmc-to-discuss-their-5-nm-cmos-technology-platform-at-iedm-2019/

At the upcoming International Electron Devices Meeting (IEDM) in San Francisco December 7-11, Geoffrey Yeap will present the talk “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and High-Mobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications”.
Details of the 5-nm (N5) process have been slowly released over the last while, most recently at the Technology Symposium in April and the Open Innovation Platform Innovation Forum (OIP) last month, both in Santa Clara. Condensing the reported information from the two, and in no particular order, we have:
• Aimed at both high-performance computing and mobile customers
• Risk production started in March 2019; high volume ramp in 2Q’20 at the recently completed Gigafab 18 in Tainan (phase 1 equipment installation completed in March’19)
• There will be a N5P (performance) version a year later, with a +7% performance boost at constant power, or ~15% power reduction at constant perf over N5
• Logic density is increased by 1.8X, SRAM scaling is 0.75, and analog scaling is ~0.85 vs 7-nm
• Iso-power speed gain is 15%, or 30% lower power at the same speed compared with 7-nm.
• EUV use was emphasised
• There will be a high-mobility channel (Ge?) transistor
• Low-resistance contacts and vias.
• Transistor variants include an I/O transistor that can be either 1.5V or 1.2V, and an extreme LVT device 25% faster than the 7-nm equivalent.
• Via pillars and optimized metal in the HPC standard cells increase performance by 10%
• A 112Gbps SerDes is available.
• A super-high-density MIM-capacitor structure with 2X ff/µm2 and 2X insertion density, giving a 4% speed boost
• New low-K dielectric materials
• Metal Reactive Ion Etching (RIE), replacing Cu damascene for metal pitch < 30nm
• A graphene “cap” to reduce Cu interconnect resistivity

My thanks to Tom Dillinger at SemiWiki and Paul McLellan of Breakfast Bytes for their diligent reportage.
In the conference abstract details published by IEDM in their press kit, much of the above is reiterated. The logic density is a more detailed 1.84X, and the same 15% speed increase or 30% power drop over their 7-nm process are specified, as is EUV lithography (Fig. 2) and the high channel-mobility FinFET (Fig. 3). In addition, there are up to 7 Vts available (Fig.1). The company also says the high-density SRAM cell is the smallest ever reported, at 0.021µm2.
In a test circuit, a PAM4 SerDes transmitter demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The technology passed qualification with high yield and mass production is expected in 1H 2020. Fig. 1 below shows the 15% speed and density gains (left), and the seven Vt options.

Figure 1

Fig. 2 illustrates the comparison of five immersion masks with a single EUV mask, in what looks like a standard cell routing layer, i.e. M1 or M2. With a tentative Mx pitch of 30 nm, that would need SAQP or LE3, plus a couple of cut masks, replaced with one EUV litho step. Using MxP of 30 nm to calibrate, this image gives us a track height of ~175 nm (~5.8 track cell), a linear scaling of ~0.73 compared with the 7-nm process. And we can see that the pattern is quite a bit sharper.

Figure 2

Fig. 3 Improved drive current in stressed high-mobility devices (left); higher stress in fin determined by e-beam diffraction (right)

Fig. 3 (above) illustrates the improved drive current (+18%) in the high-mobility-channel transistor. There has been some comment that this might be a germanium channel (fin), but given the mis-match of the crystal lattices between Ge and Si, and the dislocations that would generate, it seems more likely that we have a PMOS SiGe channel similar to that used in the planar gate-first HKMG parts from the IBM consortium, containing up to 40% Ge.
The high-magnification TEM lattice images from a fin shown above indicate that the channel is the conventional <110> direction, though strangely the diffraction image on the right seems to be taken in the <100> direction.
Fig. 4 below is simply a plot of published SRAM cell sizes, showing the 0.021µm2 SRAM is the smallest reported to date.

Figure 4

Figure 5

In Fig. 5 above we have eye diagrams for PAM4 SerDes transmitters built on a 5-nm test chip demonstrating the 112 Gb/s mentioned earlier and the 130 Gb/s detailed in the abstract.
No mention is made in the IEDM preview of some of the earlier comments on the process; new low-k dielectrics is not surprising, but the dry etching of copper metallization is – if that is implemented, to my knowledge it will be a first. Could it be an application of the evolving technique of atomic-layer etching? And we have seen graphene metal caps in the literature, but again its use will be a first.
This looks to be an exciting presentation, but you will need patience and stamina to take it in – it is paper #36.7, scheduled at 4.05 pm on Wednesday 11th, the last paper of that session and almost the last paper of the conference!

健人就是腳勤

真是大事,Global Foundry退出7nm製程競賽了!

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